1. Field
This invention relates generally to memory fabrication, and more particularly to a semiconductor processing method for flash memory fabrication.
2. Background Art
The semiconductor market has been undergoing extensive growth over the past few decades. This trend is expected to continue for the foreseeable future since a large portion of this market is the memory segment. The memory segment can be broadly categorized into two classes, namely volatile memory and non-volatile memory. Volatile memory such as SRAM and DRAM lose their data content when the power supply is removed. In contrast, non-volatile memories such as EEPROM and flash memories maintain their data content after the power supply has been removed.
Non-volatile memories offer particular advantages, and thereby support a wide range of applications including computer, automotive and consumer electronic devices. Flash memory is a non-voltage memory that can be electrically erased and reprogrammed. In fact, flash memory has undergone an explosive market growth that has in particular been driven by cellular telephones, memory cards, flash drives and other types of portable data storage devices. Indeed, with the need to support persistent data storage in portable devices, it is clear that the flash memory will continue to grow at an ever increasing rate. Further, the market place will demand flash memory designs that support lower cost and higher performance, including higher densities of storage.
The basic concept of a flash memory cell is that of a floating gate in a metal oxide semiconductor transistor. The floating gate serves as a charge storage layer, and a nitride layer can be used to form the floating gate. The electrical isolation of the floating gate is accomplished by surrounding the gate with dielectric material, such an oxide. Typically, flash memory cells use two oxide layers, a “bottom” oxide layer and a “top” oxide layer, to form a sandwich around the floating gate in the form of a dielectric stack. Because of the use of oxide layers and a nitride layer, the dielectric stack is commonly referred to as an oxide-nitride-oxide (or ONO) layer.
Data in the memory cell array is accessed by application of voltages to bit lines and word lines. The bit lines are formed on the semiconductor substrate and function as a source and a drain with an active channel region defined therebetween. The oxide-nitride-oxide (ONO) dielectric layer is formed on the top of the substrate and bit lines. The word lines are then formed on the top of the ONO layer, and perpendicular to the bit lines. Applying a voltage to the word line, which acts as a control gate, along with an applied voltage to the bit line allows for the reading or writing of data from or to that location in the memory cell array.
Between a predetermined number of word lines, conductive vias can traverse the dielectric stack to establish electrical contact to the bit lines. For bit lines made from n+-type conductivity silicon, sets of vias (one via for each bit line) can be placed at intervals of about eight to about sixteen word lines. To reduce the resistivity of the connections to the memory devices, metal silicides can be formed on the surface of electrically conductive structures (e.g., bit lines) of the memory devices.